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this document contains information on a new product. spec ifications and information herein are subject to change without notice. ? motorola, inc., 2002. all rights reserved. 1 introduction motorola?s dragonball ? family of microprocessors has demonstrated leadership in the portable handheld market. con tinuing this legacy, the drag onball mx (media extensions) series provides a leap in performance with an arm9? mi croprocessor core and highly integrated system functions. dragonball mx prod ucts specifically address the requirements of the personal, portable produ ct market by providing intellig ent integrated peripherals, an advanced processor core, and power management capabilities. the new dragonball mx1-lite (MC9328MXL) f eatures the advanced and power-efficient arm920t? core that operates at speeds up to 200 mhz. integrated modules, which include an lcd controller, usb support, and an mmc/sd host controller, support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience. it is packaged in either a 256-pin mold array process-ball grid array (mapbga) or 225-pin pbga package. figure 1 shows the functional block diagram of the MC9328MXL. figure 1. MC9328MXL functional block diagram watchdog gpio lcd controller jtag/ice cgm timer 1 & 2 pwm standard bootstrap connectivity system control i 2 c mmc/sd spi 1 and uart 1 uart 2 usb device memory stick? human interface video port multimedia multimedia power rtc bus dmac interrupt vmmu cpu complex MC9328MXL i cache aipi 1 aipi 2 d cache eim & arm9tdmi? system i/o control (pllx2) controller control (11 chnl) sdramc accelerator spi 2 host controller ssi/i 2 s advance information MC9328MXL/d rev. 2, 12/2002 MC9328MXL (dragonball? mx1-lite) integrated portable system processor contents 1 introduction . . . . . . . . . . . 1 2 signals and connections . . . . . . . . . . 4 3 specifications . . . . . . . . 10 4 pin-out and package information . . . . . . . . . . 79
2 MC9328MXL advance information motorola introduction 1.1 conventions this document uses the following conventions: overbar is used to indicate a signal that is active when pulled low: for example, reset . logic level one is a voltage that corresponds to boolean true (1) state. logic level zero is a voltage that corresponds to boolean false (0) state. to set a bit or bits means to establish logic level one. to clear a bit or bits means to establish logic level zero. a signal is an electronic construct whose state conv eys or changes in state convey information. a pin is an external physical connection. the same pi n can be used to connect a number of signals. asserted means that a discrete signal is in active logic state. ? active low signals change from logic le vel one to logic level zero. ? active high signals change from logic level zero to logic level one. negated means that an asserted discrete signal changes logic state. ? active low signals change from logic le vel zero to logic level one. ? active high signals change from logic le vel one to logic level zero. lsb means least significant bit or bits , and msb means most significant bit or bits . references to low and high bytes or words are spelled out. numbers preceded by a percent sign (%) are bina ry. numbers preceded by a dollar sign ($) or 0x are hexadecimal. 1.2 features to support a wide variety of applications, the mc9328 mxl provides a robust array of features, including the following: arm920t? microprocessor core ahb to ip bus interfaces (aipis) external interface module (eim) sdram controller (sdramc) clock generation module (c gm) and power control module two universal asynchronous receiv er/transmitters (uart 1 and uart 2) two serial peripheral interfaces (spi) two general-purpose 32-bit counters/timers watchdog timer real-time clock/sampling timer (rtc) lcd controller (lcdc) pulse-width modulation (pwm) module universal serial bus (usb) device multimedia card and secure digita l (mmc/sd) host controller module memory stick? host controller (mshc)
introduction motorola MC9328MXL advance information 3 direct memory access controller (dmac) synchronous serial interface and inter-ic sound (ssi/i 2 s) module inter-ic (i 2 c) bus module video port general-purpose i/o (gpio) ports bootstrap mode multimedia accelerator (mma) power management features operating voltage range: 1.7 v to 1.98 v core, 1.7 v to 3.3v i/o 256-pin mapbga package 1.3 target applications the MC9328MXL is targeted for ad vanced information appliances, sm art phones, web browsers, digital mp3 audio players, handheld comput ers, and messaging applications. 1.4 product documentation the following documents are required for a complete description of the MC9328MXL and are necessary to design properly with the device . especially for those not familia r with the arm920t processor or previous dragonball products , the following documents are helpful wh en used in conjun ction with this document. arm architecture reference manual (arm ltd., order number arm ddi 0100) arm9dt1 data sheet manual (arm ltd., order number arm ddi 0029) arm technical reference manual (arm ltd., order number arm ddi 0151c) emt9 technical reference manual (arm ltd., order number ddi o157e) mc9328mx1 product brief (order number mc9328mx1p/d) mc9328mx1 reference manual (order number mc9328mx1rm/d) the motorola manuals are available on th e motorola semiconductors web site at http://www.motorola.com/s emiconductors. these documents may be downloaded di rectly from the motorola web site, or printed ve rsions may be ordered. the arm documentation is available from http://www.arm.com. 1.5 ordering information table 1 provides ordering information for the 256-le ad mold array process ball grid array (mapbga) package. table 1. MC9328MXL ordering information package type frequency temperature order number 256-lead mapbga 150 mhz 0 o c to 70 o c MC9328MXL15 256-lead mapbga 200 mhz 0 o c to 70 o c MC9328MXL20
4 MC9328MXL advance information motorola signals and connections 2 signals and connections table 2 identifies and describes the MC9328MXL signal s that are assigned to package pins. the signals are grouped by the internal modu le that they are connected to. 225-lead pbga 150 mhz 0 o c to 70 o c tbd 225-lead pbga 200 mhz 0 o c to 70 o c tbd table 2. MC9328MXL signal descriptions signal name function/notes external bus/chip-select (eim) a[24:0] address bus signals d[31:0] data bus signals eb0 msb byte strobe?active low external enab le byte signal that controls d [31:24]. eb1 byte strobe?active low external enable byte signal that controls d [23:16]. eb2 byte strobe?active low external enable byte signal that controls d [15:8]. eb3 lsb byte strobe?active low external enabl e byte signal that controls d [7:0]. oe memory output enable?active low ou tput enables external data bus. cs [5:0] chip-select?the chip-select signals cs [3:2] are multip lexed with csd [1:0] and are selected by the function multiplexing co ntrol register (fmcr). by default csd [1:0] is selected. ecb active low input signal sent by a flash device to the eim whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by a flash device caus ing the external burst device to latch the starting burst address. bclk clock signal sent to external synchronous memories (such as burst flash) during burst mode. rw rw signal?indicates whether external access is a read (high) or write (low) cycle. used as a we input signal by external dram. dtack dtack signal? the external input data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by th e external dtack signal after 1022 clock counts have elapsed. table 1. MC9328MXL ordering information (continued) package type frequency temperature order number
signals and connections motorola MC9328MXL advance information 5 bootstrap boot [3:0] system boot mode select?the operational system boot mode of the MC9328MXL upon system reset is determined by the settings of these pins. sdram controller sdba [4:0] sdram/syncflash non-interleave mode bank address multiplexed with address signals a [15:11]. these signals are logically equiva lent to core address p_addr [25:21] in sdram/syncflash cycles. sdiba [3:0] sdram/syncflash interleave addressing mode bank address multiplexed with address signals a [19:16]. these signals are logically eq uivalent to core address p_addr [12:9] in sdram/syncflash cycles. ma [11:10] sdram address signals ma [9:0] sdram address signals which are multiplexed with address signals a [10:1]. ma [9:0] are selected on sdram/syncflash cycles. dqm [3:0] sdram data enable csd0 sdram/syncflash chip-select signal which is multiplexed with the cs2 signal. these two signals are selectable by progra mming the system control register. csd1 sdram/syncflash chip-select signa l which is multiplexed with cs3 signal. these two signals are selectable by programming the system control register. by default, csd1 is selected, so it can be used as syncflash b oot chip-select by properly configuring boot [3:0] input pins. ras sdram/syncflash row address select signal cas sdram/syncflash column address select signal sdwe sdram/syncflash write enable signal sdcke0 sdram/syncflash clock enable 0 sdcke1 sdram/syncflash clock enable 1 sdclk sdram/syncflash clock reset_sf syncflash reset clocks and resets extal16m crystal input (4 mhz to 16 mhz), or a 16 mhz oscillator input when the internal oscillator circuit is shut down. xtal16m crystal output extal32k 32 khz crystal input xtal32k 32 khz crystal output clko clock out signal selected from internal clock signals. table 2. MC9328MXL signal descriptions (continued) signal name function/notes
6 MC9328MXL advance information motorola signals and connections reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module and the clock control module) are reset. reset_out reset out?internal active low output signal from the watchdog timer module and is asserted from the following sources: power-on reset, exte rnal reset (reset_in ), and watchdog time-out. por power on reset?internal active high schmit t trigger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. jtag trst test reset pin?external active low signal used to asynchronously initialize the jtag controller. tdo serial output for test instructions and data. changes on the falling edge of tck. tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and cont rol register access through the jtag port. tms test mode select to sequence the jtag test controller?s state mach ine. sampled on the rising edge of tck. dma big_endian big endian?input signal that determines the configuration of the external chip-select space. if it is driven logic- high at reset, the external chip-select space will be configured to little endian. if it is driven logic-low at reset, the external chip-select space will be configured to big endian. dma_req external dma request pin. etm etmtracesync etm sync signal which is multiplexed with a24. etmtracesync is selected in etm mode. etmtraceclk etm clock signal which is multiplexed with a23. etmtraceclk is selected in etm mode. etmpipestat [2:0] etm status signals which are multiplexed with a [2 2:20]. etmpipest at [2:0] are selected in etm mode. etmtracepkt [7:0] etm packet signals which are multiplexed with ecb , lba , bclk, pa17, a [19:16]. etmtracepkt [7:0] are selected in etm mode. cmos sensor interface csi_d [7:0] sensor port data csi_mclk sensor port master clock csi_vsync sensor port vertical sync csi_hsync sensor port horizontal sync table 2. MC9328MXL signal descriptions (continued) signal name function/notes
signals and connections motorola MC9328MXL advance information 7 csi_pixclk sensor port data latch clock lcd controller ld [15:0] lcd data bus?all lcd signals are driven low after reset and when lcd is off. flm/vsync frame sync or vsync?this signal also serves as the clock signal output for the gate driver (dedicated signal sps for sharp panel hr-tft). lp/hsync line pulse or h sync lsclk shift clock acd/oe alternate crystal direction/output enable. contrast this signal is used to control the lcd bias voltage as contrast control. spl_spr program horizontal scan direction (sharp panel dedicated signal). ps control signal output for source driv er (sharp panel dedicated signal). cls start signal output for gate driver. this signal is an inverted version of ps (sharp panel dedicated signal). rev signal for common electrode driving signal preparation (sharp panel dedicated signal). spi spi1_mosi master out/slave in spi1_miso slave in/master out spi1_ss slave select (selectable polarity) spi1_sclk serial clock spi1_spi_rdy serial data ready spi2_txd spi2 master txdata output?this signal is mu ltiplexed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. please refer to the spi and gpio chapters in the MC9328MXL reference manual for information about how to bring this signal to the assigned pin. spi2_rxd spi2 master rxdata input?this signal is mult iplexed with a gpi/o pin yet shows up as a primary or alternative signal in the signal mult iplex scheme table. plea se refer to the spi and gpio chapters in the MC9328MXL reference manual for information about how to bring this signal to the assigned pin. spi2_ss spi2 slave select?this signal is multiplexed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiple x scheme table. please refer to the spi and gpio chapters in the MC9328MXL reference manual for information about how to bring this signal to the assigned pin. spi2_sclk spi2 serial clock?this si gnal is multiplexed wi th a gpi/o pin yet sh ows up as a primary or alternative signal in the signal multiple x scheme table. please refer to the spi and gpio chapters in the MC9328MXL reference manual for information about how to bring this signal to the assigned pin. table 2. MC9328MXL signal descriptions (continued) signal name function/notes
8 MC9328MXL advance information motorola signals and connections general purpose timers tin timer input capture or timer input clock?the signal on this input is applied to both timers simultaneously. tmr2out timer 2 output usb device usbd_vmo usb minus output usbd_vpo usb plus output usbd_vm usb minus input usbd_vp usb plus input usbd_suspnd usb suspend output usbd_rcv usb rxd usbd_oe usb oe usbd_afe usb analog front end enable secure digital interface sd_cmd sd command?if the system desig ner does not wish to make us e of the inte rnal pull-up, via the pull-up enable register, a 4.7k?69k external pull up resistor must be added. sd_clk mmc output clock sd_dat [3:0] data?if the system designer d oes not wish to make use of the internal pul l-up, via the pull-up enable register, a 50k?69k external pull up resistor must be added. memory stick interface ms_bs memory stick bus state (output)?serial bus control signal ms_sdio memory stick serial data (input/output) ms_sclko memory stick external clock (input)?external clock source for sclk divider ms_sclki memory stick serial clock (output)?serial pr otocol clock signal ms_pi0 general purpose input0?can be used for me mory stick insertion/extraction detect ms_pi1 general purpose input1?can be used for me mory stick insertion/extraction detect uarts ? irda/auto-bauding uart1_rxd receive data uart1_txd transmit data uart1_rts request to send uart1_cts clear to send table 2. MC9328MXL signal descriptions (continued) signal name function/notes
signals and connections motorola MC9328MXL advance information 9 uart2_rxd receive data uart2_txd transmit data uart2_rts request to send uart2_cts clear to send uart2_dsr data set ready uart2_ri ring indicator uart2_dcd data carrier detect uart2_dtr data terminal ready serial audio port ? ssi (configurable to i 2 s protocol) ssi_txdat transmit data ssi_rxdat receive data ssi_txclk transmit serial clock ssi_rxclk receive serial clock ssi_txfs transmit frame sync ssi_rxfs receive frame sync i 2 c i2c_scl i 2 c clock i2c_sda i 2 c data pwm pwmo pwm output digital supply pins nvdd digital supply for the i/o pins nvss digital ground for the i/o pins supply pins ? analog modules avdd supply for analog blocks avss quiet gnd for analog blocks internal power supply qvdd power supply pins for silicon internal circuitry table 2. MC9328MXL signal descriptions (continued) signal name function/notes
10 MC9328MXL advance information motorola specifications 3 specifications this section contains the electri cal specifications and timing diag rams for the MC9328MXL processor. 3.1 maximum ratings table 3 provides information on maximum ratings. 3.2 recommended operating range table 4 provides the recommended operating ranges for the supply voltages. the dragonball mx1-lite has multiple pairs of vdd and vss power supply and return pins. qvdd and qvss pins are used for internal logic. all other vdd and vss pins are for the i/o pads voltage supply, and each pair of vdd and vss provides power to the enclosed i/o pads. this desi gn allows different peripher al supply voltage levels in a system. because avdd pins are supply voltages to the analog pads, it is recommended to is olate and noise-filter the avdd pins from other vdd pins. for more information about i/o pads groupi ng per vdd, please refer to table 2 on page 4. qvss gnd pins for silicon internal circuitry substrate supply pins svdd supply routed through substrate of package; not to be bonded sgnd ground routed through substrate of package; not to be bonded table 3. maximum ratings rating symbol minimum maximum unit supply voltage v dd -0.3 3.3 v maximum operating temperature range t a 070 c storage temperature test -55 150 c table 4. recommended operating range rating symbol minimum maximum unit i/o supply voltage, usbd, lcd and csi are only 3v interface nvdd 1 2.70 3.30 v i/o supply voltage nvdd 2 1.70 3.30 v internal supply voltage (core = 150 mhz) qvdd 1 1.70 1.90 v internal supply voltage (core = 200 mhz) qvdd 2 1.80 2.00 v table 2. MC9328MXL signal descriptions (continued) signal name function/notes
specifications motorola MC9328MXL advance information 11 3.3 dc electrical characteristics table 5 contains both maximum and minimum dc characteristics of the MC9328MXL. analog supply voltage avdd 1.70 3.30 v table 5. maximum and minimum dc characteristics number or symbol parameter minimum typical maximum unit iop full running operating current at 1.8v (core), 3.3v i/o (core = 96 mhz, system = 96 mhz, program running in internal sram, cache disabled) ?90 ?ma sidd 1 standby current (core = 150 mhz, qvdd = 1.8v, temp = 25 c) ?25 ? a sidd 2 standby current (core = 150 mhz, qvdd = 1.8v, temp = 55 c) ?45 ? a sidd 3 standby current (core = 150 mhz, qvdd = 2.0v, temp = 25 c) ?35 ? a sidd 4 standby current (core = 150 mhz, qvdd = 2.0v, temp = 55 c) ?60 ? a v ih input high voltage 0.7v dd ? vdd+0.2 v v il input low voltage ? ? 0.4 v v oh output high voltage (i oh =2.0ma) 0.7v dd ?vddv v ol output low voltage (i ol = -2.5 ma) ? ? 0.4 v v it+ positive input thre shold voltage, v i =v ih 1.126 v v it- negative input threshold voltage, v i =v il 0.640 v v hys hysteresis (v it+ ? v it-) =v ih 0.3 i il input low leakage current (v in = gnd, no pull-up or pull-down) ??1 a i ih input high leakage current (v in =v dd , no pull-up or pull-down) ??1 a i oh output high current (v oh =0.8v dd , v dd =1.8v) 4.0 ? ? ma i ol output low current (v ol =0.4v, v dd =1.8v) ?? ? 4.0 ma table 4. recommended operating range (continued) rating symbol minimum maximum unit
12 MC9328MXL advance information motorola specifications 3.4 ac electrical characteristics the ac characteristics consist of output delays, in put setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of other signals. all timing specifications are specified at a system operating frequency from 0 mhz to 96 mhz (core operating frequency 150 mhz) with an operating supply voltage from v dd min to v dd max under an operating temperature from t l to t h . all timing is measured at pf loading. 3.5 embedded trace macrocell all registers in the etm9 are prog rammed through a jtag interface. the interface is an extension of the arm920t processor?s tap controller, and is assigned scan chain 6. the scan chain consists of a 40-bit shift register comprised of the following: 32-bit data field 7-bit address field a read/write bit the data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. a register is read by scanning its address into the a ddress field and a 0 into the read/write bit. the 32-bit data field is ignored. a read or a write takes place when the tap controller enters the update-dr state. the timing diagram for the etm9 is shown in figure 2. see table 7 on page 13 for the etm9 timing parameters used in figure 2. i oz output leakage current (v out =v dd , output is tri-stated) ??5 a c i input capacitance ? ? 5 pf c o output capacitance ? ? 5 pf table 6. tristate signal timing pin parameter minimum maximum unit tristate time from tristate activa te until i/o becomes hi-z ? 20.8 ns table 5. maximum and minimum dc characteristics (continued) number or symbol parameter minimum typical maximum unit
specifications motorola MC9328MXL advance information 13 figure 2. trace port timing diagram table 7. trace port timi ng diagram parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 clk frequency 0 85 0 100 mhz 2a clock high time 1.3 ? 2?ns 2b clock low time 3? 2?ns 3a clock rise time ?4 ?3ns 3b clock fall time ?3 ?3ns 4a output hold time 2.28 ? 2?ns 4b output setup time 3.42 ? 3?ns traceclk 4b 4a 3b 2a 1 output trace port 3a valid data valid data 2b traceclk (half-rate clocking mode)
14 MC9328MXL advance information motorola specifications 3.6 dpll timing specifications parameters of the dpll are given in table 8. in this table, t ref is a reference clock period after the pre-divider and t dck is the output double clock period. table 8. dpll specifications parameter test conditions minimum typical maximum unit reference clock freq range vcc = 1.8v 5 ? 100 mhz pre-divider output clock freq range vcc = 1.8v 5 ? 30 mhz double clock freq range vcc = 1.8v 80 ? 220 mhz pre-divider factor (pd) ? 1 ? 16 ? total multiplication factor (mf) includes both integer and fractional parts 5?15? mf integer part ?5?15? mf numerator should be less than the denominator 0 ? 1022 ? mf denominator ? 1 ? 1023 ? pre-multiplier lock-in time ? ? ? 312.5 nsec freq lock-in time after full reset fol mode for non-integer mf (does not include pre-mult lock-in time) 250 280 (56 s) 300 t ref freq lock-in time after partial reset fol mode for non-integer mf (does not include pre-mult lock-in time) 220 250 (~50 s) 270 t ref phase lock-in time after full reset fpl mode and integer mf (does not include pre-mult lock-in time) 300 350 (70 s) 400 t ref phase lock-in time after partial reset fpl mode and integer mf (does not include pre-mult lock-in time) 270 320 (64 s) 370 t ref freq jitter (p-p) ? ? 0.005 (0.01%) 0.01 2?t dck phase jitter (p-p) integer mf, fpl mode, vcc=1.8v ? 1.0 (10%) 1.5 ns power supply voltage ? 1.8 ? 2.5 v power dissipation fol mode, integer mf, f dck = 200 mhz, vcc = 1.8v ?? 4mw
specifications motorola MC9328MXL advance information 15 3.7 reset module the timing relationships of the rese t module with the por and reset_in are shown in figure 3 and figure 4. be aware that nvdd must ramp up to at least 1.8v before qvdd is powered up to prevent forward biading. figure 3. timing relationship with por figure 4. timing relationship with reset_in 14 cycles @ clk32 7 cycles @ clk32 300ms por reset_por reset_dram hreset clk32 hclk reset_out 1 4 2 3 14 cycles @ clk32 reset_in clk32 hclk 5 4 hreset reset_out 6
16 MC9328MXL advance information motorola specifications table 9. reset module timing parameter table re f no . parameter 1.8v 0.10v 3.0v 0.30v unit minim um maxim um minim um maxim um 1 width of input power_on_reset 100 ? 1 ? ns 2 width of internal power_on_reset (clk32 at 32 khz) 300 300 300 300 ms 3 7k to 32k-cycle stretcher for sdram reset 7 7 7 7 cycles of clk32 4 14k to 32k-cycle stretche r for internal system reset hresert and output reset at pin reset_out 14 14 14 14 cycles of clk32 5 width of external hard-reset reset_in 4?4? cycles of clk32 6 4k to 32k-cycle qualifier 4 4 4 4 cycles of clk32
specifications motorola MC9328MXL advance information 17 3.8 external interface module the external interface module (e im) handles the interface to devi ces external to the MC9328MXL, including the generation of chip-sel ects for external peripherals and memory. the timing diagram for the eim is shown in figure 5, and table 10 on page 18 defines the parameters of signals. figure 5. eim bus timing diagram 1a 1b 2a 2b 3b 3a 4a 4b 4c 4d 5a 5b 5c 5d 6a 6a 6b 6c 7a 7b 7c 8a 8b 9b 9c 9a 9a 7d (hclk) bus clock address chip-select read (write ) oe (rising edge) lba (negated rising edge) oe (falling edge) burst clock (rising edge) lba (negated falling edge) eb (falling edge) eb (rising edge) burst clock (falling edge) read data write data (negated falling) write data (negated rising) dtack_b 10a 10a
18 MC9328MXL advance information motorola specifications table 10. eim bus timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit min typical max min typical max 1a clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns 1b clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns 2a clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns 2b clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns 3a clock fall to read (write ) valid 1.352.796.52 1.3 2.7 6.3 ns 3b clock fall to read (write ) invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns 4a clock 1 rise to output enable valid 1. clock refers to the system clock signal , hclk, generated from the system pll 2.32 2.62 6.85 2.3 2.6 6.8 ns 4b clock 1 rise to output enab le invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns 4c clock 1 fall to output enable valid 2.38 2.69 7.04 2.3 2.6 6.8 ns 4d clock 1 fall to output enab le invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns 5a clock 1 rise to enable bytes valid 1.91 2.52 5.54 1.9 2.5 5.5 ns 5b clock 1 rise to enable bytes invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns 5c clock 1 fall to enable bytes valid 1.97 2.59 5.69 1.9 2.5 5.5 ns 5d clock 1 fall to enable bytes invalid 1.76 2.48 5.38 1.7 2.4 5.2 ns 6a clock 1 fall to load burst address valid 2.07 2.79 6.73 2.0 2.7 6.5 ns 6b clock 1 fall to load burst address invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns 6c clock 1 rise to load burst address invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns 7a clock 1 rise to burst clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns 7b clock 1 rise to burst clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns 7c clock 1 fall to burst clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns 7d clock 1 fall to burst clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns 8a read data setup time 5.54 ? ? 5.5 ? ? ns 8b read data hold time 0 ? ? 0?? ns 9a clock 1 rise to write data valid 1.81 2.72 6.85 1.8 2.7 6.8 ns 9b clock 1 fall to write data invalid 1.45 2.48 5.69 1.4 2.4 5.5 ns 9c clock 1 rise to write data invalid 1.63 ? ? 1.62 ? ? ns 10a dtack setup time 2.52 ? ? 2.5 ? ? ns
specifications motorola MC9328MXL advance information 19 3.8.1 dtack signal description the dtack signal is the external inpu t data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out moni tor generates a bus error when a bus cycle is not terminated by the external dtack signal after 1022 hclk counts have elapsed. only cs5 group will support dtack signal function when using the external dtack signal for data acknowledgement. 3.8.2 dtack signal timing figure 6 shows the access cycle timing used by chip-sel ect 5. the signal values and units of measure for this figure are found in table 11. figure 6. dtack timing , wsc=111111, dtack_sel=0 table 11. access cycle timing parameters ref no. characteristic 1.8v 0.10v 3.0v 0.30v unit min max min max 1cs5 asserted to oe asserted ?t?tns 2 external dtack input setup from cs5 asserted 0?0?ns 3cs5 pulse width 3t ? 3t ? ns 4 external dtack input hold after cs5 is negated 0 1.5t 0 1.5t ns 5oe negated after cs5 is negated 0 4.5 0 4 ns cs5 rw oe ext_dtack hclk int_dtack 1 2 3 4 5
20 MC9328MXL advance information motorola specifications figure 7. dtack timing , wsc=111111, dtack_sel=1 note: 1. n is the number of wait st ates in the current memory access cycle. the max n is 1022. 2. t is the system clock period (system clock is 96 mhz). 3. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. table 12. access cycle timing parameters ref no. characteristic 1.8v 0.10v 3.0v 0.30v unit minimum maximu m minimum maximu m 1 external dtack input setup from cs5 asserted 0?0?ns note: 1. n is the number of wait states in the current memory access cycle. the max n is 1022. 2. t is the system clock period (system clock is 96 mhz). 3. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. table 11. access cycle ti ming parameters (continued) ref no. characteristic 1.8v 0.10v 3.0v 0.30v unit min max min max cs 5 rw oe ext_dtack (wait ) hclk int_dtack 1
specifications motorola MC9328MXL advance information 21 3.8.3 eim external bus timing the following timing diagrams show the timing of accesses to memory or a peripheral. figure 8. wsc = 1, a.half/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready bclk a[24:0] cs [0] r/w lba oe eb (ebc=0) eb (ebc=1) ss data_in read seq/nonseq v1 last valid data last valid address read v1 v1 v1
22 MC9328MXL advance information motorola specifications figure 9. wsc = 1, wea = 1, wen = 1, a.half/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready hwdata weim_hready bclk a[24:0] cs [0] r/w lba oe eb ss d[31:0] write nonseq v1 last valid data last valid address weim_hrdata write data (v1) unknown last valid data v1 write last valid data write data (v1)
specifications motorola MC9328MXL advance information 23 figure 10. wsc = 1, oea = 1, a.word/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [0] r/w lba oe eb (ebc=1) ss data_in weim_hrdata eb (ebc=0) read nonseq v1 last valid data address v1 v1 word read address v1 + 2 last valid addr 1/2 half word 2/2 half word
24 MC9328MXL advance information motorola specifications figure 11. wsc = 1, wea = 1, wen = 2, a.word/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [0] r/w lba oe eb ss d[31:0] weim_hrdata hwdata write nonseq v1 last valid data address v1 write data (v1 word) write address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data
specifications motorola MC9328MXL advance information 25 figure 12. wsc = 3, oea = 2, a.word/e.half hclk hselm_weim_cs[3] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [3] r/w lba oe eb (ebc=0) ss data_in weim_hrdata eb (ebc=1) read nonseq v1 last valid data address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word read
26 MC9328MXL advance information motorola specifications figure 13. wsc = 3, wea = 1, wen = 3, a.word/e.half hclk hselm_weim_cs[3] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [3] r/w lba oe ss d[31:0] weim_hrdata eb hwdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data
specifications motorola MC9328MXL advance information 27 figure 14. wsc = 3, oea = 4, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read
28 MC9328MXL advance information motorola specifications figure 15. wsc = 3, wea = 2, wen = 3, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss d[31:0] hwdata eb weim_hrdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data
specifications motorola MC9328MXL advance information 29 figure 16. wsc = 3, oen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read
30 MC9328MXL advance information motorola specifications figure 17. wsc = 3, oea = 2, oen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read
specifications motorola MC9328MXL advance information 31 figure 18. wsc = 2, wws = 1, wea = 1, wen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss weim_hrdata eb d[31:0] hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) last valid data write
32 MC9328MXL advance information motorola specifications figure 19. wsc = 1, wws = 2, wea = 1, wen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss weim_hrdata eb d[31:0] hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data
specifications motorola MC9328MXL advance information 33 figure 20. wsc = 2, wws = 2, wea = 1, wen = 2, a.half/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss d[31:0] weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 write data address v8 last valid addr last valid data read write nonseq v8 last valid data read data write read data last valid data write data hwdata data_in
34 MC9328MXL advance information motorola specifications figure 21. wsc = 2, wws = 1, wea = 1, wen = 2, edc = 1, a.half/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr read data last valid data read write nonseq v8 d[31:0] hwdata last valid data write data read data write last valid data write data read write idle
specifications motorola MC9328MXL advance information 35 figure 22. wsc = 2, csa = 1, wws = 1, a.word/e.half write nonseq v1 address v1 address v1 + 2 last valid addr last valid data write data (word) write last valid data last valid data write data (1/2 half word) w rite data (2/2 half word) hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [3:0] r/w lba oe ss weim_hrdata eb d[31:0] hwdata
36 MC9328MXL advance information motorola specifications figure 23. wsc = 3, csa = 1, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr last valid data read last valid data read data write data write nonseq v8 write read data write data last valid data d[31:0] hwdata
specifications motorola MC9328MXL advance information 37 figure 24. wsc = 2, oea = 2, cnc = 3, bcm = 1, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 read data (v1) address v2 last valid addr last valid data read read seq v2 idle read data (v2) cnc read data (v1) read data (v2)
38 MC9328MXL advance information motorola specifications figure 25. wsc = 2, oea = 2, wea = 1, wen = 2, cnc = 3, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr read data last valid data read d[31:0] hwdata write nonseq v8 idle last valid data write data read data write cnc last valid data write data
specifications motorola MC9328MXL advance information 39 figure 26. wsc = 1, wea = 1, wen = 1, shen = 01 or shen = 10, a.half/e.half write data (i3) hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) d[31:0] hwdata ahb_hrdata read write read write read write read data read data (e1) read read read write write write nonseq nonseq nonseq nonseq nonseq nonseq idle e1 i1 e2 i2 i3 i4 l a st we i m_h r d a t a read data e1 read data (i2) read data (i4) write data (i1) last valid data write data (e2) last valid data last valid addr address e1 address i1 address i2 address i3 address i4 address e2 last valid data i1 data i2 data i3 data i4 data write data (e2)
40 MC9328MXL advance information motorola specifications figure 27. wsc = 1, wea = 1, wen = 1, edc = 2, shen = 01, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) d[31:0] hwdata nonseq nonseq nonseq nonseq nonseq nonseq idle read read read write write write e1 i1 e2 i2 i3 i4 read data (e1) l a st we i m_ hr d a t a read data (e1) read data (i2) read data (i4) write data (i1) last valid data write data (e2) last valid data read write read write last valid addr address e1 address i2 address i3 address i4 address e2 read data last valid data i2 data i3 data i4 data write data (e2) ahb_hrdata dead cycles write data (i3)
specifications motorola MC9328MXL advance information 41 figure 28. wsc = 1, wea = 1, wen = 1, edc = 2, shen = 10, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) d[31:0] hwdata ahb_hrdata nonseq nonseq nonseq nonseq nonseq nonseq idle read read read write write write e1 i1 e2 i2 i3 i4 read data (e1) last we i m_h r d a ta read data (e1) read data (i2) read data (i4) write data (i1) last valid data write data (e2) last valid data read write read write last valid addr address e1 address i1 address i3 address i4 address e2 read data last valid data i2 data i3 data i4 data write data (e2) write data (i3) address i2 write read i1 data dead cycles
42 MC9328MXL advance information motorola specifications figure 29. wsc = 3, sync = 1, a.half/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) nonseq nonseq read read idle v1 v5 address v1 last valid addr address v5 read v1 word v2 word v5 word v6 word ecb
specifications motorola MC9328MXL advance information 43 figure 30. wsc = 2, sync = 1, dol = [1/0], a.word/e.word hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb nonseq seq read idle v1 seq seq read read read v2 v3 v4 last valid data v1 word v2 word v3 word v4 word address v1 last valid addr read v1 word v2 word v3 word v4 word
44 MC9328MXL advance information motorola specifications figure 31. wsc = 2, sync = 1, dol = [1/0], shen = 01, a.word/e.word hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb nonseq seq read idle v1 seq seq read read read v2 v3 v4 last valid data v1 word v2 word v3 word v4 word address v1 last valid addr read v1 word v2 word v3 word v4 word address v2 address v3 address v4
specifications motorola MC9328MXL advance information 45 figure 32. wsc = 2, sync = 1, do l = [1/0], shen = 10, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb nonseq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last valid addr read v1 1/2 v1 2/2 v2 1/2 v2 2/2 address v2 address v1+2 address v2+2
46 MC9328MXL advance information motorola specifications figure 33. wsc = 2, sync = 1, dol = [1/0], a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb address v1 last valid addr read v1 1/2 v1 2/2 v2 1/2 v2 2/2 address v2 nonseq seq read idle v1 read v2 last valid data v1 word v2 word
specifications motorola MC9328MXL advance information 47 figure 34. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 2, a.word/e.half non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last valid addr read v1 1/2 v1 2/2 v2 1/2 v2 2/2 hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb
48 MC9328MXL advance information motorola specifications figure 35. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 1, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe ss data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last valid addr read v1 1/2 v1 2/2 v2 1/2 v2 2/2
specifications motorola MC9328MXL advance information 49 3.9 spi timing diagrams to utilize the internal transmit (tx) and receive (rx) data fifos when the spi 1 module is configured as a master, two control signals are used for data transfer rate control: the ss signal (output) and the spi_rdy signal (input). the spi 1 sample period control register (periodreg1) and the spi 2 sample period control register (per iodreg2) can also be programmed to a fixed data transfer rate for either spi 1 or spi 2. when the spi 1 module is conf igured as a slave, the user can configure the spi 1 control register (controlreg1) to match the external spi master?s timing. in this configuration, ss becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data fifo. figure 36 through figure 40 show the timing relationship of the master spi using different tr iggering mechanisms. . figure 36. master spi timing diagram using spi_rdy edge trigger figure 37. master spi timing diagram using spi_rdy level trigger figure 38. master spi timing diagram ignore spi_rdy level trigger figure 39. slave spi timing diag ram fifo advanced by bit count 1 2 3 5 4 ss spirdy sclk, mosi, miso ss spirdy sclk, mosi, miso sclk, mosi, miso ss (output) ss (input) sclk, mosi, miso
50 MC9328MXL advance information motorola specifications figure 40. slave spi timing diagram fifo advanced by ss rising edge 3.10 lcd controller this section includes timing diagra ms for the lcd controller. for de tailed timing diagrams of the lcd controller with various display configurations , refer to the lcd controller chapter of the MC9328MXL reference manual . figure 41. sclk to ld timing diagram table 13. timing parameter table for figure 36 through figure 40 ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum m inimum maximum 1 spi_rdy to ss output low 2t 1 1. t = cspi system clo ck period (perclk2). ? 2t 1 ?ns 2 ss output low to first sclk edge 3 tsclk 2 2. tsclk = period of sclk. ? 3 tsclk 2 ?ns 3 last sclk edge to ss output high 2 tsclk ? 2 tsclk ? ns 4 ss output high to spi_rdy low 0?0?ns 5ss output pulse width tsclk + wait 3 3. wait = number of bit clocks (s clk) or 32.768 khz clocks per sa mple period co ntrol register. ? tsclk + wait 3 ?ns 6 ss input low to first sclk edge t?t?ns 7ss input pulse width t ? t ? ns 6 7 ss (input) sclk, mosi, miso 1 lsclk ld[15:0]
specifications motorola MC9328MXL advance information 51 figure 42. 4/8/16 bit/pixe l tft color mode panel timing table 14. lcdc sclk timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sclk to ld valid ? 2 ? 2 ns table 15. 4/8/16 bit/pixe l tft color mode panel timing symbol description minimum corresponding register value unit t1 end of oe to beginning of vsyn t5+t6 +t7+t9 (vwait1t2)+t5+t6+t7+t9 ts t2 hsyn period xmax+5 xma x+t5+t6+t7+t9+t10 ts t3 vsyn pulse widt h t2 vwidth(t2) ts t4 end of vsyn to beginning of oe 2 vwait2(t2) ts t5 hsyn pulse width 1 hwidth+1 ts t6 end of hsyn to beginning to t9 1 hwait2+1 ts line 1 line y t1 t4 t3 (1,1) (1,2) (1,x) t5 t7 t6 xmax vsyn hsyn oe ld[15:0] sclk hsyn oe ld[15:0] t2 t8 vsyn t9 t10 display region non-display region line y
52 MC9328MXL advance information motorola specifications t7 end of oe to beginning of hsyn 1 hwait1+1 ts t8 sclk to valid ld data -3 3 ns t9 end of hsyn idle2 to vsyn edge (for non-display region) 22ts t9 end of hsyn idle2 to vsyn edge (for display region) 11ts t10 vsyn to oe active (sharp = 0), when vwait2 = 0 11ts t10 vsyn to oe active (sharp = 1) when vwait2 = 0 22ts note: ts is the sclk period which equals lcdc_clk / (pcd + 1). normally lcdc_clk = 15ns. vsyn, hsyn and oe can be programmed as active high or active low. in figure 42, all 3 signals are active low. the polarity of sclk and ld[15:0] can also be programmed. sclk can be programmed to be deactivated during the vsyn pulse or the oe deasserted period. in figure 42, sclk is always active. for t9 non-display region, vsyn is non-active. it is used as an reference. xmax is defined in pixels. table 15. 4/8/16 bit/pixel tft color mode panel timing (continued) symbol description minimum corresponding register value unit
specifications motorola MC9328MXL advance information 53 3.11 multimedia card/secure digital host controller the dma interface block controls all data routing be tween the external data bus (dma access), internal mmc/sd module data bus, and internal system fifo access through a dedicated state machine that monitors the status of fifo content (empty or full) , fifo address, and byte/block counters for the mmc/ sd module (inner system) and th e application (user programming). figure 43. chip-select read cycle timing diagram table 16. sdhc bus timing parameter table ref no. parameter 1.8v 0.10v 3.0 0.30v unit minimum maximum minimum maximum 1 clk frequency at data transfer mode (pp) 1 ?10/30 cards 1. c l 100 pf / 250 pf (10/30 cards) 0 25/5 0 25/5 mhz 2 clk frequency at identification mode 2 2. c l 250 pf (21 cards) 0 400 0 400 khz 3a clock high time 1 ?10/30 cards 6/33 ? 10/50 ? ns 3b clock low time 1 ?10/30 cards 15/75 ? 10/50 ? ns 4a clock fall time 1 ?10/30 cards ? 10/50 (5.00) 3 ?10/50 ns 4b clock rise time 1 ?10/30 cards ? 14/67 (6.67) 3 ?10/50 ns 5a input hold time 3 ?10/30 cards 3. c l 25 pf (1 card) 5.7/5.7 ? 5/5 ? ns 5b input setup time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 6a output hold time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 6b output setup time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 7 output delay time 3 016 014 ns bus clock 5b 6b 6a 7 5a 4a 3a 1 cmd_dat input cmd_dat output 4b 3b valid data valid data valid data valid data 2
54 MC9328MXL advance information motorola specifications 3.11.1 command respon se timing on mmc/sd bus the card identification and card oper ation conditions timing are processe d in open-drain mode. the card response to the host comm and starts after exactly n id clock cycles. for the card address assignment, set_rca is also processed in the open-drain mode . the minimum delay between the host command and card response is ncr clock cycles as illustrated in figure 44. the symbols for fi gure 44 through figure 48 are defined in table 17. figure 44. timing diagra ms at identification mode after a card receives its rca, it switches to data transfer mode. as shown on the first diagram in figure 45, sd_cmd lines in this mo de are driven with push-pull driv ers. the command is followed by a period of two z bits (allowing time for direction switching on the bus) and then by p bits pushed up by the responding card. the other two diagrams show the separating periods n rc and n cc . table 17. state signal parameters for figure 44 through figure 48 card active host active symbol definition symbol definition z high impedance state s start bit (0) d data bits t transmitter bit (host = 1, card = 0) * repetition p one-cycle pull-up (1) crc cyclic redundancy check bits (7 bits) e end bit (1) set_rca timing identification timing host command cid/ocr n id cycles cmd content s t e z z s t content z z ****** crc z host command cid/ocr n cr cycles cmd content s t e z z s t content z z ****** crc z
specifications motorola MC9328MXL advance information 55 figure 45. timing diagrams at data transfer mode figure 46 on page 56 shows basic read operation timing. in a read operation, th e sequence starts with a single block read command (which specifies the start ad dress in the argument field). the response is sent on the sd_cmd lines as usual. data transmission from the card starts after the access time delay n ac , beginning from the last bit of the read command. if the sy stem is in multiple block read mode, the card sends a continuous flow of data blocks with distance n ac until the card sees a stop transmission command. the data stops two clock cycles afte r the end bit of the stop command. timing of command sequences (all modes) timing response end to next cmd start (data transfer mode) command response timing (data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z z ****** crc z response host command n rc cycles cmd content s t e z z s t content crc e z z ****** crc z host command host command n cc cycles cmd content s t e z z s t content crc e z z ****** crc z
56 MC9328MXL advance information motorola specifications figure 46. timing diagrams at data read figure 47 shows the basic write operat ion timing. as with the read opera tion, after the card response, the data transfer starts after n wr cycles. the data is suffixed with crc check bits to allo w the card to check for transmission errors. the card send s back the crc check result as a cc status token on the data line. if there was a transmission error, the card sends a ne gative crc status (101); otherwise, a positive crc status (010) is returned. the card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command. n ac cycles read data timing of single block read n ac cycles read data timing of multiple block read n ac cycles n st timing of stop command (cmd12, data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc dat z****z z z p p s d ***** d d d dat z****z z z p p s d ***** ****** d d d p ***** p s d d d d ****** host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc ***** read data host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc valid read data dat ***** z z e ***** d d d d d d d d z
specifications motorola MC9328MXL advance information 57 figure 47. timing diagrams at data write write data busy write data write data host command response n cr cycles cmd dat timing of the block write command n wr cycles busy crc status cmd dat timing of the multiple block write command content crc status n wr cycles crc status e z z p p p p ****** z z p p s crc e z z s e z p p s content crc e z z s e s e z x x x x x x l*l x x x x x x status status dat content z z p p s crc e z z x x z p p s content crc e z z x x x x x x x x x x z n wr cycles x x x x x x z****z z z z p p s content crc e z z s e s e z l*l status x x x x x x x z x x x e z z p p s content crc z z z dat z****z content s t crc e z z p p s t content crc e z z p ****** ****** p p p
58 MC9328MXL advance information motorola specifications the stop transmission command may occur when the ca rd is in different stat es. figure 48 shows the different scenarios on the bus. figure 48. stop transmission during different scenarios write data stop transmission during data transfer from the host. busy (card is programming) stop transmission during crc status transfer from the card. stop transmission received after last data block. card becomes busy programming. stop transmission received after last data block. card becomes busy programming. host command card response n cr cycles cmd content s t e z z p p s t content crc e z z ****** host command content s t crc e dat ****** d d d d d d z z z z d d d d d d d e z z s l z z z z z z z z z z z z z z z z z z z z z z e dat ****** d d d d d d z z z z d z z s z z s l z z z z z z z z z z z z z z z z z z z z z z e crc e crc dat ****** s l z z z z z z z z z z z z z z z z z z z z z z z z z z e dat ****** z z z z z z z z z z z z z z z z z z z z s l z z z z z z z z z z z z z z z z z z z z z z e z
specifications motorola MC9328MXL advance information 59 3.11.2 sdio-irq and re adwait service handling in sdio, there is a 1-bit or 4-bit interrupt response from the sdio peripheral card. in 1-bit mode, the interrupt response is simply that the sd_dat[1] line is held low. the sd_dat[1] line is not used as data in this mode. the memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (s d_dat[1] returns to its high level). in 4-bit mode, the interrupt is less simple. the interrupt triggers at a pa rticular period called the "interrupt period" during the data access, and the controller must sample sd_dat[1] during this short period to determine the irq status of the attached card. the in terrupt period only happens at the boundary of each block (512 bytes). table 18. timing values for figure 44 through figure 48 parameter symbol minimum maximum unit parameter mmc/sd bus clock, clk (all values are referred to minimum (vih) and maximum (vil) mmc/sd bus clock, clk (all values are referred to minimum (vih) and maximum (vil) command response cycle ncr 2 64 clock cycles command response cycle identification response cycle nid 5 5 clock cycles identification response cycle access time delay cycle nac 2 taac + nsac clock cycles access time delay cycle command read cycle nrc 8 ? clock cycles command read cycle command-command cycle ncc 8 ? clock cycles command-command cycle command write cycle nwr 2 ? clock cycles command write cycle stop transmission cycle nst 2 2 clock cycles stop transmission cycle taac: data read access time -1 defined in csd register bit[119:112] nsac: data read access time -2 in clk cycles (nsac100) defined in csd register bit[111:104] taac: data read access time -1 defined in csd register bit[119:112] nsac: data read access time -2 in clk cycles (nsac100) defined in csd register bit[111:104]
60 MC9328MXL advance information motorola specifications figure 49. sdio irq timing diagram readwait is another feature in sdio that allows the us er to submit commands during the data transfer. in this mode, the block temporarily paus es the data transfer operation coun ter and related status, yet keeps the clock running, and allows the user to submit commands as normal. af ter all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues. figure 50. sdio readwait timing diagram 3.12 memory stick host controller the memory stick protocol requires three interface signal line connec tions for data transfers: ms_bs, ms_sdio, and ms_sclko (or ms_scl ki). communication is always initiated by the mshc and operates the bus in either four-state or two-state access mode. the ms_bs signal classifies data on the sdio into one of four states (bs0, bs1, bs2, or bs3) according to its attribute and transfer direction. bs0 is the in t transfer state, and duri ng this state no packet transmissions occur. during the bs1, bs2, and bs3 st ates, packet communications are executed. the bs1, bs2, and bs3 states are regarded as one packet length and one communica tion transfer is always completed within one packet length (in fo ur-state access mode). the memory stick usually operates in four state acces s mode and in bs1, bs2, and bs3 bus states. when an error occurs during packet comm unication, the mode is shifted to two-state access mode, and the bs0 and bs1 bus states are automatically repeat ed to avoid a bus collision on the sdio. interrupt period irq irq dat[1] for 4-bit l h interrupt period dat[1] for 1-bit cmd content s t e z z p e z z ****** z z response crc s z z e s block data e s block data dat[1] for 4-bit dat[2] for 4-bit cmd ****** p s t e z z ****** cmd52 z crc e z z s block data l l l l l l l l l l l l l l l l l l l l l h z s e s block data e block data z z l h e s block data
specifications motorola MC9328MXL advance information 61 figure 51. mshc si gnal timing diagram table 19. mshc signal timing parameter table ref no. parameter 3.0 0.3v unit minimum maximum 1 ms_sclki frequency ? 25 mhz 2 ms_sclki high pulse width 20 ? ns 3 ms_sclki low pulse width 20 ? ns 4 ms_sclki rise time ? 3 ns 5 ms_sclki fall time ? 3 ns 6 ms_sclko frequency 1 ?25mhz 7 ms_sclko high pulse width 1 20 ? ns 8 ms_sclko low pulse width 1 15 ? ns 9 ms_sclko rise time 1 ?5ns ms_sclko 11 ms_bs ms_sdio(output) ms_sdio (input) ms_sdio (input) 11 12 12 13 14 15 16 (red bit = 0) (red bit = 1) ms_sclki 1 6 2 3 7 8 4 5 9 10
62 MC9328MXL advance information motorola specifications 10 ms_sclko fall time 1 ?5ns 11 ms_bs delay time 1 ?3ns 12 ms_sdio output delay time 1,2 ?3ns 13 ms_sdio input setup time for ms_sclko rising edge (red bit = 0) 3 18 ? ns 14 ms_sdio input hold time for ms_sclko rising edge (red bit = 0) 3 0?ns 15 ms_sdio input setup time for ms_sclko falling edge (red bit = 1) 4 23 ? ns 16 ms_sdio input hold time for ms_sclko falling edge (red bit = 1) 4 0?ns 1. loading capacitor condition is less than or equal to 30pf. 2. an external resistor (100 ~ 200 ohm) should be insert ed in series to provide current control on the ms_sdio pin, because of a possibi lity of signal conflict between the ms_sdio pin and memory stick sdio pin when the pin direction changes. 3. if the msc2[red] bit = 0, mshc samples ms _sdio input data at ms_sclko rising edge. 4. if the msc2[red] bit = 1, mshc samples ms_sdio input data at ms_sclko falling edge. table 19. mshc signal timing parameter table (continued) ref no. parameter 3.0 0.3v unit minimum maximum
specifications motorola MC9328MXL advance information 63 3.13 pulse-width modulator the pwm can be programmed to select one of two clock signals as its source frequency. the selected clock signal is passed through a divider and a prescaler before being input to th e counter. the output is available at the pulse-width modulator output (pwm o) external pin. its timing diagram is shown in figure 52 and the parameters are listed in table 20. figure 52. pwm output timing diagram 3.14 sdram controller a write to an address within the memory region in itiates the program sequence. the first command issued to the syncflash is load command register. a [7:0 ] determine which operatio n the command performs. for this write setup operation, an address of 0x40 is hardware generate d. the bank and other address lines are driven with the address to be programmed. th e next command is active which registers the row address and confirms the bank address. the third co mmand supplies the column address, re-confirms the bank address, and su pplies the data to be written. syncflash do es not support burst writes, therefore a burst terminate comman d is not required. a read to the memory region initiate s the status read sequence. the firs t command issued to the syncflash is the load command register with a [7:0] set to 0x70 which corresponds to the read status register operation. the bank and other address lines are driven to the selected address. the second command is table 20. pwm output timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 system clk frequency 1 1. c l of pwmo = 30 pf 0870100mhz 2a clock high time 1 3.3 ? 5/10 ? ns 2b clock low time 1 7.5 ? 5/10 ? ns 3a clock fall time 1 ?5?5/10ns 3b clock rise time 1 ? 6.67 ? 5/10 ns 4a output delay time 1 5.7 ? 5 ? ns 4b output setup time 1 5.7 ? 5 ? ns system clock 2a 1 pwm output 3b 2b 3a 4b 4a
64 MC9328MXL advance information motorola specifications active which sets up the status register read. the ba nk and row addresses are driven during this command. the third command of the triplet is read. bank and column addresses ar e driven on the address bus during this command. data is re turned from memory on the low order 8 data bits following the cas latency. figure 53. sdram/syncflas h read cycle timing diagram table 21. sdram ti ming parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.6 ?4? ns 2 sdram clock low-level width 6? 4? ns 3 sdram clock cycle time 11.4 ? 10 ? ns 3s cs, ras, cas, we, dqm setup time 3.42 ? 3? ns sdclk cs cas we ras addr dq dqm row/ba col/ba 3s 3h 3s 3h 3s 3 s 3h 3h 3h 4s 4h 5 3s 3 2 1 8 data 7 6
specifications motorola MC9328MXL advance information 65 note: cke is high during the read/write cycle. 3h cs, ras, cas, we, dqm hold time 2.28 ? 2? ns 4s address setup time 3.42 ? 3? ns 4h address hold time 2.28 ? 2? ns 5 sdram access time (cl = 3) ? 6.84 ?6 ns 5 sdram access time (cl = 2) ? 6.84 ?6 ns 5 sdram access time (cl = 1) ? ? ?? ns 6 data out hold time 2.85 ? 2.5 ? ns 7 data out high-impedance time (cl = 3) ? 6.84 ?6 ns 7 data out high-impedance time (cl = 2) ? 6.84 ?6 ns 7 data out high-impedance time (cl = 1) ? ? ?? ns 8 active to read/write command period (rc = 1) t rcd ? t rcd ? ns table 21. sdram timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
66 MC9328MXL advance information motorola specifications figure 54. sdram/syncflash write cycle timing diagram table 22. sdram write timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.66 ? 4? ns 2 sdram clock low-level width 6? 4? ns 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3? ns 5 address hold time 2.28 ? 2? ns 6 precharge cycle period t rp ? t rp ? ns 7 active to read/write command delay t rcd ? t rcd ? ns 8 data setup time 2.28 ? 2? ns sdclk cs cas we ras addr dq dqm / ba row/ba 3 4 6 1 col/ba data 2 5 7 8 9
specifications motorola MC9328MXL advance information 67 note: precharge cycle timing is includ ed in the write timing diagram. figure 55. sdram refresh timing diagram 9 data hold time 2.28 ? 2? ns table 23. sdram refresh timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4? ns 2 sdram clock low-level width 6? 4? ns 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3? ns table 22. sdram write timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum sdclk cs cas we ras addr dq dqm ba 3 4 6 1 2 5 7 row/ba 7
68 MC9328MXL advance information motorola specifications figure 56. sdram self-refresh cycle timing diagram 5 address hold time 2.28 ? 2? ns 6 precharge cycle period t rp ? t rp ? ns 7 auto precharge command period t rc ? t rc ? ns table 23. sdram refresh timi ng parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum sdclk cs cas ras addr dq dqm ba we cke
specifications motorola MC9328MXL advance information 69 3.15 usb device port four types of data transfer modes exist for the usb mo dule: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. from the perspective of the usb modu le, the interrupt transfer type is identical to the bulk data transfer mode, and no additional ha rdware is supplied to su pport it. this section covers the transfer modes and ho w they work from the ground up. data moves across the usb in packets. groups of pack ets are combined to form data transfers. the same packet transfer mechanism applies to bulk, interrupt, an d control transfers. isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the usb bandwidth at all times, there is no end-of-transfer. figure 57. usb device timing diagram for data transfer to usb transceiver (tx) table 24. usb device timing parameter table for data transfer to usb transceiver (tx) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 t roe_vpo ; usbd_roe active to usbd_vpo low 83.14 83.47 83.14 83.47 ns 2 t roe_vmo ; usbd_roe active to usbd_vmo high 81.55 81.98 81.55 81.98 ns 3 t vpo_roe ; usbd_vpo high to usbd_roe deactivated 83.54 83.80 83.54 83.80 ns usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) usbd_suspnd (output) usbd_rcv (input) usbd_vp (input) usbd_vm (input) t roe_vpo t vmo_roe t vpo_roe t feopt t roe_vmo t period 1 2 3 4 5 6
70 MC9328MXL advance information motorola specifications figure 58. usb device timing diagram for data transfer from usb transceiver (rx) 4 t vmo_roe ; usbd_vmo low to usbd_roe deactivated (includes se0) 248.90 249.13 248.90 249.13 ns 5t feopt ; se0 interval of eop 160.00 175.00 160.00 175.00 ns 6t period ; data transfer rate 11.97 12.03 11.97 12.03 mb/s table 25. usb device timing parameter table for data transfer from usb transceiver (rx) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1t feopr ; receiver se0 interval of eop 82 ? 82 ? ns table 24. usb device timing parameter table for data transfer to usb transceiver (tx) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) (output) usbd_suspnd (input) usbd_vp usbd_rcv (input) usbd_vm (input) t feopr 1
specifications motorola MC9328MXL advance information 71 3.16 i 2 c module the i 2 c communication protocol consists of seven el ements: start, data source/recipient, data direction, slave acknowledge, da ta, data acknowl edge, and stop. figure 59. definition of bus timing for i 2 c 3.17 synchronous serial interface the transmit and receive sections of the ssi can be synchronous or asynchrono us. in synchronous mode, the transmitter and the receiver use a common clock an d frame synchronization signal. in asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. continuous or gated clock mode can be selected. in continuous mode, the clock runs continuously. in gated clock mode, the clock functions only during transmission. the internal and external clock timing diagrams are shown in figure 61 through figure 63 on page 73. normal or network mode can also be selected. in no rmal mode, the ssi functions with one data word of i/o per frame. in network mode, a frame can contain between 2 and 32 data words. network mode is typically used in star or ring-tim e division multiplex networks with ot her processors or codecs, allowing interface to time division multiplexed networks withou t additional logic. use of the gated clock is not allowed in network mode. th ese distinctions result in the basic op erating modes that allow the ssi to communicate with a wide variety of devices. table 26. i 2 c bus timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 hold time (repeated) start condition 182 ? 160 ? ns 2 data hold time 0171 0150 ns 3 data setup time 11.4 ? 10 ? ns 4 high period of the scl clock 80 ? 120 ? ns 5 low period of the scl clock 480 ? 320 ? ns 6 setup time for stop condition 182.4 ? 160 ? ns sda scl 1 2 3 4 6 5
72 MC9328MXL advance information motorola specifications note: srxd input in synchronous mode only. figure 60. ssi transmitter internal clock timing diagram figure 61. ssi receiver internal clock timing diagram stck output stfs (bl) output stfs (wl) output 1 2 6 8 10 11 stxd output srxd input 32 31 4 12 srck output srfs (bl) output srfs (wl) output 3 7 srxd input 13 14 1 5 9
specifications motorola MC9328MXL advance information 73 figure 62. ssi transmitter external clock timing diagram figure 63. ssi receiver ex ternal clock timing diagram table 27. ssi (port c primary function) timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum internal clock operation 1 (port c primary function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.5 4.5 1.3 3.9 ns 3 srck high to srfs (bl) high 3 -1.2 -1.7 -1.1 -1.5 ns stck input 16 stfs (bl) input stfs (wl) input 17 18 22 24 26 stxd output srxd input 27 28 34 note: srxd input in synchronous mode only 33 20 15 srck input 16 srfs (bl) input srfs (wl) input 17 19 23 srxd input 29 30 21 25 15
74 MC9328MXL advance information motorola specifications 4 stck high to stfs (bl) low 3 2.5 4.3 2.2 3.8 ns 5 srck high to srfs (bl) low 3 0.1 -0.8 0.1 -0.8 ns 6 stck high to stfs (wl) high 3 1.48 4.45 1.3 3.9 ns 7 srck high to srfs (wl) high 3 -1.1 -1.5 -1.1 -1.5 ns 8 stck high to stfs (wl) low 3 2.51 4.33 2.2 3.8 ns 9 srck high to srfs (wl) low 3 0.1 -0.8 0.1 -0.8 ns 10 stck high to stxd valid from high impedance 14.25 15.73 12.5 13.8 ns 11a stck high to stxd high 0.91 3.08 0.8 2.7 ns 11b stck high to stxd low 0.57 3.19 0.5 2.8 ns 12 stck high to stxd high impedance 12.88 13.57 11.3 11.9 ns 13 srxd setup time before srck low 21.1 ? 18.5 ? ns 14 srxd hold time after srck low 0 ? 0? ns external clock operation (port c primary function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ?92.8 081.4 ns 19 srck high to srfs (bl) high 3 ?92.8 081.4 ns 20 stck high to stfs (bl) low 3 ?92.8 081.4 ns 21 srck high to srfs (bl) low 3 ?92.8 081.4 ns 22 stck high to stfs (wl) high 3 ?92.8 081.4 ns 23 srck high to srfs (wl) high 3 ?92.8 081.4 ns 24 stck high to stfs (wl) low 3 ?92.8 081.4 ns 25 srck high to srfs (wl) low 3 ?92.8 081.4 ns 26 stck high to stxd valid from high impedance 18.01 28.16 15.8 24.7 ns 27a stck high to stxd high 8.98 18.13 7.0 15.9 ns 27b stck high to stxd low 9.12 18.24 8.0 16.0 ns table 27. ssi (port c primary functi on) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
specifications motorola MC9328MXL advance information 75 28 stck high to stxd high impedance 18.47 28.5 16.2 25.0 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hole time after srck low 0 ? 0 ? ns synchronous internal clock operation (port c primary function 2 ) 31 srxd setup before stck falling 15.4 ? 13.5 ? ns 32 srxd hold after stck falling 0 ? 0? ns synchronous external clock operation (port c primary function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. 2. there are 2 sets of i/o signals for the ssi module. they are from port c primary function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288 ). when ssi signals are configured as outputs, they can be viewed both at port c primary function and port b alternate function. when ssi signals are configured as input, the ssi module selects the inpu t based on status of the fm cr register bits in the clock controller module (crm). by default, the input are selected from port c primary function. 3. bl = bit length; wl = word length. table 28. ssi (port b alternat e function) timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum internal clock operation 1 (port b altern ate function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.7 4.8 1.5 4.2 ns 3 srck high to srfs (bl) high 3 -0.1 1.0 -0.1 1.0 ns 4 stck high to stfs (bl) low 3 3.08 5.24 2.7 4.6 ns 5 srck high to srfs (bl) low 3 1.25 2.28 1.1 2.0 ns 6 stck high to stfs (wl) high 3 1.71 4.79 1.5 4.2 ns 7 srck high to srfs (wl) high 3 -0.1 1.0 -0.1 1.0 ns 8 stck high to stfs (wl) low 3 3.08 5.24 2.7 4.6 ns table 27. ssi (port c primary functi on) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
76 MC9328MXL advance information motorola specifications 9 srck high to srfs (wl) low 3 1.25 2.28 1.1 2.0 ns 10 stck high to stxd valid from high impedance 14.93 16.19 13.1 14.2 ns 11a stck high to stxd high 1.25 3.42 1.1 3.0 ns 11b stck high to stxd low 2.51 3.99 2.2 3.5 ns 12 stck high to stxd high impedance 12.43 14.59 10.9 12.8 ns 13 srxd setup time before srck low 20 ? 17.5 ? ns 14 srxd hold time after srck low 0 ? 0? ns external clock operation (port b alternate function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.9 29.07 16.6 25.5 ns 27a stck high to stxd high 9.23 20.75 8.1 18.2 ns 27b stck high to stxd low 10.60 21.32 9.3 18.7 ns 28 stck high to stxd high impedance 17.90 29.75 15.7 26.1 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hold time after srck low 0 ? 0? ns table 28. ssi (port b alternate funct ion) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
specifications motorola MC9328MXL advance information 77 3.18 cmos sensor interface the csi module consists of a cont rol register to configure the inte rface timing, a control register for statistic data generation, a status register, interface logic, a 32 32 image data receive fifo, and a 16 32 statistic data fifo. figure 64 shows the timing di agram when the cmos sensor output data is configured for negative edge and the cs i is programmed to receiv ed data in positive edge. the parameters for the timing diagram are listed in table 29 on page 78. figure 64. csi signal timing diagram synchronous internal clock operation (port b alternate function 2 ) 31 srxd setup before stck falling 18.81 ? 16.5 ? ns 32 srxd hold after stck falling 0 ? 0? ns synchronous external clock operation (port b alternate function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0? ns 1. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. 2. there are 2 set of i/o signals for the ssi module. they are from port c primary function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288 ). when ssi signals are configured as outputs, they can be viewed both at port c primary function and port b alternate function. when ssi signals are configured as inputs, the ssi module selects the input based on fmcr register bits in the clock controller module (crm). by default, the input are selected from port c primary function. 3. bl = bit length; wl = word length. table 28. ssi (port b alternate funct ion) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum csi_pixclk 4b 4a 3a 2a 1 csi_hsync/csi_d 3b 2b csi_vsync valid_data 5
78 MC9328MXL advance information motorola specifications table 29. csi signal timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 csi_pixclk frequency 0 48 048 mhz 2a csi_pixclk high time 1 1. c l 30 pf 10.42 ? 10.42 ? ns 2b csi_pixclk low time 1 10.42 ? 10.42 ? ns 3a csi_pixclk fall time 1 ?5 ?1 ns 3b csi_pixclk rise time 1 ?6.67 ?1 ns 4a csi_hsync/csi_d hold time 1 1? 1? ns 4b csi_hsync/csi_d setup time 1 1? 1? ns 5 csi_vsync to data valid time 1 200 ? 200 ? ns
pin-out and package information motorola MC9328MXL advance information 79 4 pin-out and package information table 30 illustrates the package pin a ssignments for the 256-pin mapbga package. table 30. MC9328MXL 256 mapbga pin assignments 12345678910111213141516 a vss sd_dat3 sd_clk vss usbd_af e nvdd4 vss uart1_r ts uart1_r xd nvdd3 bt5 bt3 qvdd4 rvp uip rm b a24 sd_dat1 sd_cmd sim_tx usbd_o e usbd_vp ssi_rxc lk ssi_txc lk spi1_scl k bt11 bt7 bt1 vss rvm uin rp c a23 d31 sd_dat0 sim_pd usbd_r cv uart2_c ts uart2_r xd ssi_rxf s uart1_t xd btrfgn d bt8 btrfvd d rvm1 avdd2 vss r1b d a22 d30 d29 sim_sve n usbd_s uspnd usbd_vp o usbd_v mo ssi_rxd at spi1_spi _rdy bt13 bt6 dac_om rvp1 mim r1a r2b e a20 a21 d28 d26 sd_dat2 usbd_v m uart2_r ts ssi_txd at spi1_ss bt12 bt4 dac_op mip py2 px2 r2a f a18 d27 d25 a19 a16 sim_rst uart2_t xd ssi_txf s spi1_mis o bt10 bt2 rev py1 px1 lsclk spl_spr g a15 a17 d24 d23 d21 sim_rx sim_clk uart1_c ts spi1_mo si bt9 cls contra st acd/oe lp/ hsync flm/ vsync ld1 h a13 d22 a14 d20 nvdd1 nvdd1 vss vss qvdd1 ps ld0 ld2 ld4 ld5 ld9 ld3 j a12 a11 d18 d19 nvdd1 nvdd1 vss nvdd1 vss vss ld6 ld7 ld8 ld11 qvdd3 vss k a10 d16 a9 d17 nvdd1 vss vss nvdd1 nvdd2 nvdd2 ld10 ld12 ld13 ld14 tmr2ou t ld15 l a8 a7 d13 d15 d14 nvdd1 vss cas tck tin pwmo csi_mcl k csi_d0 csi_d1 csi_d2 csi_d3 m a5 d12 d11 a6 sdclk vss rw ma10 ras reset_i n big_endi an csi_d4 csi_hsy nc csi_vsy nc csi_d6 csi_d5 n a4 eb1 d10d7a0d4pa17d1dqm1 reset_s f reset_o ut boot2 csi_pixc lk csi_d7 tms tdi p a3 d9 eb0 cs3 d6 ecb d2 d3 dqm3 sdcke1 boot3 boot0 trst i2c_scl i2c_sda xtal32k r eb2 eb3 a1 cs4 d8 d5 lba bclk d0 dqm0 sdcke0 por boot1 tdo qvdd2 extal32 k t vss a2 oe cs5 cs2 cs1 cs0 ma11 dqm2 sdwe clko avdd1 tristat e extal16 m xtal16m vss
80 MC9328MXL advance information motorola table 31 illustrates the package pin a ssignments for the 225-pin pbga package. table 31. MC9328MXL 225 pbga pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a cm d ssi1_rx clk ssi1_tx clk usbd_r oe usbd_sus pnd usbd_v m ssi0_rx fs ssi0_tx clk spi1_rd y spi1_sc lk rev ps ld2 ld4 ld5 b da t3 clk ssi1_rx dat usbd_a fe usbd_rcv usbd_v mo ssi0_rx dat uart1_t xd spi1_ss lsclk spl_s pr ld0 ld3 ld6 ld7 c d31 dat0 ssi1_rx fs ssi1_tx fs dat2 usbd_v po uart2_r xd ssi0_txf s uart1_r ts contr ast vsyn c ld8 ld9 ld12 nvdd2 d a23 a24 dat1 ssi1_tx dat nvdd1 usbd_v p qvdd4 uart2_t xd nvdd3 spi1_m osi hsyn c ld1 ld11 tout2 ld13 e a21 a22 d30 d29 nvdd1 qvss uart2_r ts uart1_r xd uart1_c ts spi1_mi so oe_a cd ld10 tin csi_d0 csi_mcl k f a20 a19 d28 d27 nvdd1 nvdd1 uart2_c ts ssi0_rx clk ssi0_txd at cls qvdd 3 ld14 ld15 csi_d2 csi_d4 g a17 a18 d26 d25 nvdd1 nvss nvdd4 nvss nvss qvss pwmo csi_d3 csi_d7 csi_hsyn c csi_d5 h a15 a16 d23 d24 d22 nvss nvss nvss nvss nvdd2 csi_d 1 csi_vsy nc csi_pixc lk i2c_data tms j a14 a12 d21 d20 nvdd1 nvss nvss qvdd1 nvss csi_d6 i2c_c lk tck tdo_b boot1 boot0 k a13 a11 cs2_b d19 nvdd1 nvss qvss nvdd1 nvss d1 boot 2 tdi big_end ian reset_ou t_b xtal32k l a10 a9 d17 d18 nvdd1 nvdd1 cs5_b d2 ecb_b nvss nvss por qvss xtal16m extal32 k m d16 d15 d13 d10 eb3_b nvdd1 cs4_b cs1_b bclk rw_b nvss boot3 qvdd2 reset_in_ b extal16 m n a8 a7 d12 eb0_b d9 d8 cs3_b cs0_b pa17 d0 dqm2 dqm0 sdcke0 tristate trst_b p d14 a5 a4 a3 a2 a1 d6 d5 ma10 ma11 dqm1 ras_b sdcke1 clko resets f_b r a6 d11 eb1_b eb2_b oe_b d7 a0 sdclk d4 lba_b d3 dqm3 cas_b sdwe_b avdd1
pin-out and package information motorola MC9328MXL advance information 81 4.1 mapbga package dimensions figure 65 illustrates the mapbga 14 mm 14 mm 1.30 mm package, which has 0.8 mm spacing between the pads. the device design ator for the mapbga package is vh. figure 65. MC9328MXL mapbga mechanical drawing top view bottom view side view notes: 1. all dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14 5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane is defined by spherical crowns of the solder balls.
82 MC9328MXL advance information motorola pin-out and package information 4.2 pbga (225) package dimensions figure 66 illustrates the 225 pb ga 13 mm 13 mm 0.8 mm package. figure 66. MC9328MXL pbga 225 mechanical drawing top view bottom view side view notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14 5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane is defined by spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package.
motorola MC9328MXL advance information 83 notes
MC9328MXL/d how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minat o-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or inte grated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or spec ifications can and do vary in di fferent applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against a ll claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. all other product or service names are the property of their respective owners. the bluetooth trademarks are owned by their proprietor and used by motorola, inc. under license. arm and the arm powered logo are the registered trademarks of arm limited. arm9, arm920t, and arm9tdmi are trademarks of arm limited. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002

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